The Double Data Rate (DDR) interface is a very popular source synchronous interface which is widely used in the integrated circuit (IC) industry and in networking products. For a DDR interface, the limiting factor of its operating frequency is clock jitter, clock duty cycle distortion and the skews within the data bus. A standard single-ended DDR interface is depicted in FIG. 1.
The skew is the variation of the transition point for all signals which are referenced to the same clock signal. The variation can be caused by difference loadings, crosstalk from neighbor signals, ISI (Inter-Symbol Interference), SSO/SSI (Simultaneous Switching Output/Input) noise, difference in propagation path lengths, and/or difference in the rise and fall time of the signal. Clock jitter is a variation in the frequency (or phase) of a clock signal due to instability of the clock source, noises coupled from power supply, and/or crosstalk from other signals. Because the DDR latches the data at both rising and falling edges, the duty cycle distortion could have a directly impact on DDR operation.
Based on industry publications and SI analysis by the assignee of the present application, simultaneous switching noise (SSN) due to simultaneous switching of input signals (SSI) and output signals (SSO) has a significant contribution to the clock jitter and data switching uncertainty. The SSI and SSO cause a spike in the quiescent drain current (IDDQ) which in turn causes a spike in the quiescent drain voltage noise (VDDQ_noise). The larger the IDDQ spike the greater the VDDQ_noise, and the larger impact on signal switching uncertainty.
In current designs, it is very common to see that the timing uncertainty due to SSO and SSI noise could be +/−250 ps to +/−350 ps separately on a 250 Mhz and a 125 Mhz DDR interface. Combining the timing uncertainty for SSO and SSI together could result in a total timing uncertainty of +/−500 ps to +/−700 ps from SSN and which is the largest portion of DDR timing budget.
The VDDQ_noise can be reduced by lowering the resistance and inductance of the IDDQ path. Thus, one way to reduce the SSO/SSI noise is to increase the number of power and ground pins supplying VDDQ current to the I/O buffers, thus reducing the signal pins to power/ground pins ratio. However, due to package size limitation and cost consideration, this is no longer an effective solution for large sized ASICs.
The System Packet Interface Level 4, Phase 2 (SPI4.2) Specification utilizes differential signaling and a dynamic clock alignment circuit (DAC) at the receiver. This interface is depicted in FIG. 2. The differential signaling could significantly reduce the SSO/SSI noise, and the DAC circuit could compensate some part of fixed data skews within the signal lines, so SPI4.2 can be operated at higher frequency. The main drawback for SPI4.2 is its differential signaling which doubles the total number of pins compared with single-ended signaling.
FIG. 2 depicts a transmitter side 2 that utilizes a 2× clock to clock data on the rising edge of the clock, so it can avoid duty cycle distortion requirement on 1× clock which is not shown in this patent. On the receiver 4 side a DAC 6 generates phase-shifted clock signals utilized to sample the data. The clock signal phases are optimized so that data is latched in the center of the data window. The DAC also compensates the fixed skew between received data signals, which could be caused by different trace length and process variation cross the interface.
Accordingly, techniques for reducing SSN without increasing total number of pins on an IC are greatly needed in the field.